The present invention relates to a field-effect transistor and a manufacturing method thereof.
With the recent development of communication devices centering around portable telephones, field-effect transistors, particularly MESFETs each having a semi-insulating substrate composed of gallium arsenide (GaAs) (hereinafter referred to as GaAs MESFETs), have been in greater demand because of their high performance. Among these, such FETs as a GaAs MESFET using an epitaxial film and a MISFET (Metal Insulator Semiconductor FET) which exhibits an improved voltage resistance due to an undoped layer formed immediately below a gate electrode with no impurity mixed therein have found wide applications as microwave communication devices.
The latest technology trends in these MESFETs and MISFETs are to achieve low-power operation and to reduce power consumption. In increasing performance during low-power operation, in particular, an improvement in the rising of FETs, i.e., a reduction in ON resistance, is the most effective. Although a reduction in gate length is the most effective method of reducing the ON resistance, it is also a significant method to lower a parasitic resistance component by reducing the distance between a source electrode and a drain electrode.
Below, the structure of a conventional FET with such a structure will be described with reference to drawings.
FIG. 12 shows a cross-sectional structure in the direction of gate length of a conventional GaAs MESFET disclosed in Japanese Laid-Open Patent Publication No. 2-156544. In the drawing are shown: a semi-insulating substrate 1 composed of GaAs; a conductive layer 2 composed of n-type GaAs doped with Si as an impurity; contact regions 3 composed of n.sup.+ -type InGaAs highly doped with Si; ohmic electrodes 4 each serving as a drain electrode or a source electrode; a gate electrode 5 composed of a Schottky electrode; wiring layers 6 formed on the ohmic electrodes 4 simultaneously with the formation of the gate electrode 5; and sidewall barriers 7 composed of SiO.sub.2, which have been formed to obtain a gate length shorter than the opening width of the ohmic electrodes 4.
Below, a description will be given to a method of manufacturing the GaAs MESFET with the above structure.
Initially, the conductive layer 2 is formed on the semi-insulating substrate 1 by epitaxial growth, followed by the formation of the contact layer serving as the contact regions 3 on the conductive layer 2 by epitaxial growth. Then, a first metal layer serving as the ohmic electrodes 4 is formed on the contact layer by sputtering or by vapor deposition, followed by etching with respect to the first metal layer to form an opening trench extending in the direction of gate width (in the direction perpendicular to the surface of the paper in FIG. 12), thereby forming the pair of ohmic electrodes 4 opposed to each other. Subsequently, wet etching is performed with respect to the above contact layer and conductive layer 2 using the pair of ohmic electrodes 4 as a mask, thereby forming an opening 8 having a cross section in the shape of an inverted mesa. Next, a SiO.sub.2 film is formed over the entire surface by plasma CVD, followed by reactive ion etching performed with respect to the SiO.sub.2 film, thereby forming the sidewall barriers 7. Next, a second metal layer is deposited by sputtering or vapor deposition, thereby forming the wiring layers 6. As a result, the metal film is deposited even inside the opening 8 using the ohmic electrodes 4 and sidewall barriers 7 as a mask, so that the gate electrode 5 having a length equal to the size of the trench between the barriers 7 is formed by self alignment.
With the above structure, however, although it is possible to form the wiring layers 6 connected to the ohmic electrodes 4, it is impossible to form a wiring layer or a contact region connected to the gate electrode 5, so that the gate electrode 5 cannot be withdrawn to the outside of the field-effect transistor. Hence, the fabrication of the field-effect transistor with the above structure is practically difficult.
In a power-type field-effect transistor or the like, on the other hand, source regions and drain regions are alternately disposed like a comb. In manufacturing such a comb-type field-effect transistor, therefore, the source regions and drain regions composing the above field-effect transistor should be formed separately, which incurs an increase in chip size.
Moreover, according to the above manufacturing method, the process of forming the sidewall barriers 7 composed of SiO.sub.2 is complicated, so that it is practically difficult to form the above sidewall barriers 7. Furthermore, in forming the sidewall barriers 7 by performing reactive ion etching with respect to the SiO.sub.2 film formed over the entire surface, the region of the conductive layer 2 in which the gate electrode 5 is to be formed is damaged and hence the channel region of the field-effect transistor is also damaged, so that the voltage resistance of the field-effect transistor is significantly lowered.